FIG. 1 shows a typical memory cell which is used for example in a dynamic random access memory (DRAM). The memory cell has a capacitance 100 or a cell capacitance for storing charges, in which information items can be stored, and a transistor 102, which preferably has a field-effect transistor, for driving the capacitance 100. The transistor 102 is also referred to as selection transistor or cell transistor and is used for reading charges into the capacitance 100 and for reading charges from the capacitance 100. During a process of writing charges to the capacitance 100 or a write operation the transistor 102 is opened with the aid of a control voltage VPP at a control input 104 of said transistor, e.g. at the gate of the field-effect transistor, and a logic low level or a local 0 or a logic high level or a logic 1 is written to the capacitance 100. Afterward, the transistor 102 is closed, and the information is stored. In order to read out the information, the transistor 102 is opened again, and the stored charge can be evaluated. In order to amplify the very small charge or voltage stored in the capacitance 100, a differential amplifier 106 is furthermore provided outside the memory cell, which amplifier compares the voltage across the capacitance 100 with a reference voltage VREF and amplifies it.
The transistors used in memory cells are usually NPN field-effect transistors, which are turned on in the event of a logic high level of a respective control voltage VPP, present at the control input or the gate terminal of the transistor. Since the charge to be read out in the capacitance of the memory cell only leads to very small voltage differences of typically 10–30 mV at the differential amplifier, the control voltage VPP at the control input of the transistor is raised by means of the normal internal voltage VINT of the memory cell or of the memory module having the memory cell. This measure leads to a very small resistance of the NPN field-effect transistor and prevents, for the most part, the small voltage present across the capacitance from being dropped across the transistor. The voltage drop of typically 300–500 mV which normally occurs at the transistor is therefore reduced
The raising of the control voltage VPP at the control input of the transistor in order to reduce the resistance thereof is usually carried out by a charge pump which generates a control voltage VPP which typically even lies above the supply voltage or the external voltage VEXT of a memory module. Usual values for the external voltage VEXT at the memory module, for the internal voltage VINT in the memory module and for the raised control voltage VPP are VEXT=2.5 V, VINT=1.8 V and VPP=3.4 V.
FIG. 2 shows a typical memory cell which is driven by a charge pump. The memory cell has, as in FIG. 1, a capacitance 200 for storing charges and a transistor 202 for writing charges to the capacitance 200 and for reading charges from the capacitance 200. The transistor 202 has a control input 204, at which a control voltage VPP can be applied in order to block or enable the writing-in or reading-out of charges. The transistor 202 is typically a field-effect transistor having a gate terminal as control input, a source terminal as input and a drain terminal as output. The input of the transistor 202 is connected to the capacitance 200, and the output of the transistor 202 is connected to a differential amplifier 206. For the operation of the differential amplifier 206, the latter is supplied with the module-internal voltage VINT, which is generated from the external voltage VEXT or supply voltage of the memory module by a generator 208. The internal voltage VINT is usually less than or equal to the external voltage VEXT. The generator 208 furthermore generates a reference voltage VREF for the differential amplifier 206, the voltage across the capacitance 200 being compared with said reference voltage.
The line which connects the transistor 202 to the differential amplifier 206 is usually referred to as bit line (BL). The differential amplifier 206, which is also called read/write amplifier, therefore serves for identifying and amplifying a very small voltage difference on the bit line. The control input 204 of the transistor 202 is connected to a row select line 210 or a word line (WL) which drives the transistor 202. This row select line 210 assumes a logic high level whenever the corresponding row of the memory module is addressed by a row select circuit 212. If the corresponding row is not addressed, then there is a logic low level on the row select line 210. A logic high level on the row select line 210 opens the transistor 202, so that the charge stored on the capacitance 200 can alter the value on the bit line. In this case, it is important, as mentioned, that as little voltage as possible is dropped across the transistor 200. This is achieved by means of a comparatively high control voltage VPP at the control input 204 of the transistor 202. A good value for the control voltage VPP lies above the value of the external voltage VEXT. The value of VPP is defined by the technology, such as e.g. the gate thickness, etc., with which a memory module is fabricated. In order to generate the high control voltage VPP a charge pump 214 is furthermore shown in FIG. 2, said charge pump being used to generate the control voltage VPP from the low external voltage VEXT.
The charge pump 214 is connected by an input thereof to the external voltage VEXT, while an output thereof is connected to the row select line 210, in a manner allowing disconnection by the row select circuit 212. The charge pump 214 or a VPP network, having the charge pump 214 supplies all the row select lines of all the memory cells which are situated in a memory module with the voltage VPP. A VPP network thus comprises, in principle, all the word lines of a memory module, and the word lines comprise several thousands, of word lines, depending on the architecture and storage capacity of the memory module. All the selection transistors of the memory module are attached, in turn, to the word lines. In a 256M memory module, by way of example, 256×1 024×1 024 transistors are attached to the word lines and thus, in principle, to the VPP network. Of course, only a small portion of the selection transistors will ever be driven simultaneously, i.e. supplied with the control voltage VPP at the gale thereof. Each time a new row is activated, the voltage VPP is applied to a row select line WL, and the connected transistors draw current from the VPP network or the charge pump 214. The current at the VPP network behaves in a manner dependent on how often such activation of a row select line takes place per unit time. For high operating frequencies of the memory module, such activation operations take place more often per unit time, and it is evident that at a high operating frequency, a VPP network or the charge pump 214 must supply more power, i.e. more charge per unit time or current. A maximum current is established in the VPP network at the maximum operating frequency of the memory module.
FIGS. 3A and 3B show the construction and the function of a typical charge pump. The charge pump is connected to the external voltage VEXT and supplies, at its output, the control voltage VPP for example for the transistor 202 in FIG. 2. The charge pump has a first capacitance 316 and a second capacitance 318 and a first group of switches 320, 322 and a second group of switches 324, 326, 327.
FIG. 3A shows a charging operation of the charge pump or of the capacitances 316 and 318. During the charging operation, the capacitances are connected in parallel with one another by the closing of the switches 324, 326, 327 and by the opening of the switches 320, 322 and are charged with the external voltage VEXT in parallel with one another. By contrast, FIG. 3B shows a discharging operation, during which the charge pump outputs the charge taken up and supplies the generated control voltage VPP to a transistor. During the discharging operation, the capacitances 316 and 318 are connected in series with one another by the opening of the switches 324, 326, 327 and by the closing of the switches 320, 322, in order to supply a voltage which is greater than the external voltage VEXT.
The charging operation and the discharging operation are carried out periodically until the desired voltage level of the control voltage VPP is established, the charge pump then being deactivated. If the value of the control voltage VPP falls below a specific value, then the charge pump is activated again on the basis of a threshold comparison. The time interval between two charging operations is determined by a clock. This clock must be chosen optimally. On the one hand, the clock must be as high as possible in order that the VPP network is charged as rapidly as possible and, during charge flow, the VPP network is held at the desired voltage level thereof; on the other hand, a specific maximum frequency of the clock must not be exceeded, in order that the charge pump can still function properly.
FIG. 4 shows a charge pump 414 and the typical construction of a drive arrangement for the charge pump 414. The charge pump 414 is supplied with the external voltage VEXT and supplies the control voltage VPP at its output. The drive arrangement 414 of the charge pump has an oscillator 426, which feeds to the charge pump 414 a charging control frequency fCC 430 or a clock which temporally controls the charging of the charge pump 414, such as e.g. the capacitances in FIG. 3. The oscillator 428 is a circuit element which is additionally provided in a memory module and which generates a defined charging control frequency which cannot be varied. This charging control frequency is typically fixed at a frequency which precisely enables the charge pump to generate, at the maximum operating frequency of a memory module or chip, a sufficient charge or stable control voltage VPP for all of the driven memory cells in the memory module. Therefore, the oscillator 428 is designed precisely for this maximum operating frequency in terms of circuitry.
The drive arrangement for the charge pump 414 furthermore has a regulator 432, which activates the charging of the charge pump if the control voltage VPP of a transistor of a memory cell or the control voltage VPP of the transistors of memory cells of a memory module falls below a specific reference voltage VREF. To that end, the regulator 432 has an input for the control voltage VPP and an input for the reference voltage VREF. The charge pump 414 and the charging of the charge pump 414 are typically controlled by means of an on/off signal 434, which can activate and deactivate both the charge pump 414 and the oscillator 428.
FIG. 5 shows the power of a charge pump from FIG. 3 as a function of the charging control frequency fCC of an oscillator, such as e.g. the oscillator 428 in FIG. 4, which temporally controls the charge pump. The curve of the power P shows that the power P is higher, the higher the frequency fCC. However, starting from a specific maximum charging control frequency fMAX, the power of the charge pump dips, which, with reference to FIG. 3, is determined on the one hand by temporal superposition of charging that is still being carried out and the capacitances already being connected in parallel, and on the other hand by excessively short periods of time available for the charging operation and the discharging operation. This point of the maximum frequency fad can be determined by simulation of the entire VPP pump. The oscillator is designed in such a way that it supplies an oscillator frequency or charging control frequency which lies just before the truncation of the power P of the charge pump and is assigned to the maximum operating frequency fCLK of the memory module and the power demand or the control voltage demand of the memory cells at this maximum operating frequency fCLK. The charging control frequency fCC supplied is lower than the maximum charging control frequency fMAX, in order that the maximum charging control frequency fMAX is not exceeded in the event of frequency fluctuations as a result of the technology, the temperature and as a result of supply voltage fluctuations. The oscillator can only supply this defined charging control frequency, irrespective of the operating frequency with, which a memory module is actually operated.
One disadvantage of a drive arrangement for a charge pump as is shown in FIG. 4 therefore consists in the fact that the oscillator 428 drives the charge pump 414 with a defined charging control frequency which is assigned to a maximum operating frequency of a memory module in order to supply sufficient voltage at this maximum operating frequency. Thus, at lower operating frequencies or varying lower operating frequencies of the memory module, the charge pump 414 generates too much charge and the entire circuit therefore consumes too much current in these cases.
U.S. Pat. No. 6,584,032 to Fujioka et al. discloses an internal voltage generator. The internal voltage generator generates an internal voltage to be supplied to an internal circuit. A predetermined amount of power is needed for operating the internal voltage generator. The internal voltage generator can be inactivated by an entry circuit, which is controlled by a control signal from the exterior. The power consumption can be reduced. Depending on the control signal from the exterior, a chip can enter a low power consumption mode.
U.S. Pat. No. 6,396,324 to Hsu et al. discloses a clock system, which is able to use an external system clock for driving a charge circuit of a semiconductor memory unit for restoring and refreshing a data area of the memory unit. The clock system comprises a plurality of control circuits, an internal clock generator circuit and a multiplexer. The multiplexer outputs either the external system clock or the internal system clock to a charge circuit according to a control signal, which is transmitted by a central processing unit to the clock system.
A further disadvantage is that chip area is taken up by the oscillator which is to be additionally accommodated in the memory module and is provided for the temporal control of the charge pump.